HLS - High Level Synthesis, FPGA, C/C++, VHDL
One of our core capabilities is the design of FPGA-based signal processing solutions. While standard components such as FIR filters are available in vendor-specific libraries, other components, e.g.
- CIC filters
- IIR filters
- non-linear functions (sine, cosine)
have to be developed individually. Direct implementation in VHDL or Verilog is a tedious task. Hence, we make use of high-level synthesis. This allows us to specify and verify an algorithm in C/C++. A HLS compiler then generates VHDL or Verilog code based on this behavioural description. This hardware description code is later used in the common FPGA design flow.