Gain

The serial gain presented here uses an amplification factor with a norm greater than one. The multiplicands a and b are used in binary representation again. However b is a constant amplification factor. Summarized, multiplication means the partial product P⁽ⁱ⁾ is added up in n steps

P^{(i + 1)} = (P⁽ⁱ⁾ + a_i ^. b) div 2 with P⁽⁰⁾ = 0 (5)

For this reason the i-th product bit p_i results from

p_i = (P⁽ⁱ⁾ + a_i ^. b) mod 2 with P⁽⁰⁾ = 0 (6)

The operations mod and div are realized by a right shift. As a result the LSB is put out. P⁽ⁿ⁾ = 0 is required after n steps or an overflow emerges, which can be detected during operation. For a_i = 1 b must be added to P⁽ⁱ⁾. If a_i = 0 an 0 is added and then all bits are shifted. This corresponds to the Booth-algorithm and has been used for implementation. To implement this algorithm some advantages can be used. The term in brackets in equations 5 and 6 is implemented only once. Its multiplication can be written

$$\sum_{j=0}^{n-1}$$ (7)

and then reduced to a conjunction of the bits originated by the binary number presentation. Figure 2 shows the gain's structure.

Condition P⁽ⁿ⁾ = 0 requires the AND gates between the adders. These prevents the LSB to be affected from the previously computed MSB. Calculation of the Sync-signal is made in the same manner like with the adder (equ. 4).

Figure 2: Serial gain