Adder

Figure 1: Serial Adder

The serial adder's structure is showed here as an example. Using the binary number representation, both summands are given as

a = $\sum_{i=0}^{n-1}$a_i ^. 2ⁱ and b = $\sum_{i=0}^{n-1}$b_i ^. 2ⁱ

with the processing word width n.

The sum results from

s_i = (a_i + b_i + c_{i - 1}) mod 2 (1)

with the carry

c_i = (a_i + b_i + c_{i - 1}) div 2 (2)

considering

c₀ = (a₀ + b₀) div 2 (3)

because there is no carry in this initial situation. At the adder's input a tuple a_i, b_i appears at each rising clock edge. At the same moment the previously sum and carry bit are stored in the D-flip-flops (fig. 1). This assures that the carry affects the sum bit's computation one clock later. The multiplexor controlling the carry FF ensures equation 3. Therefore it is switched to put out an 0 while c_{n - 1} is transmitted on the output of the part for the carry's computation.

Each bit of the sum can be processed in the following elements. As a result, an operand is handled in a distributed manner, which conforms a pipeline. This kind of adder consumes a very small amount of logic. It takes only two FFs and about 15 gates. Detecting an overflow or underflow needs determination of the word's boundary. Therefore a Sync-signal j_Adder has to be chosen from a Sync-bus (see section 4). This can be achieved by calculating the signal's constant delay in bit flow.

j_Adder = (Delay + n - 1) mod n (4)