In this place synchronization means aligning bits to the same significance and marking any bit of an operand. Generally, hardware solutions execute parallel information processing. Therefore different signal chains can lead to different delays. That means, a certain operator can receive operands with different delays.
Accordingly, there is a bus with a width of n. A signal becomes active only for one clock cycle on each line. This offers a possibility to label any bit of the word, what happens by passing the signal's delay to the component. With this information a unit selects a given Sync-signal from the bus as given for example by equ. 4.
Depending on the known signal's delay it is possible to detect a difference of delays within a component, which has more than one input. The difference can be used to insert additional delay stages in the less delayed data stream (see figure 6). This method provides a simple way to synchronize data streams, if necessary.Dsx ( Dsui manipulated variable in fig. 4), the constant delays of the operators Dox ( Doa adder delay) and additional delay stages Dgx ( Dgxk, Dgsz at adder) needed for synchronization in the operators. This is linked with a set of valid ranges for the delay stages and a sum over all of them:
can be used to find a solution via minimization methods see (Bronstein, 1991). Quantifying the delays shall be shown by an example for the integrator shown in fig. 4.
The delay block has the task to delay a sample for one clock period. Therefore the output's signal delay would be greater than the processing word width n and leads to additional delay stages at the other adder's input. This can be avoided by aligning to the prior word via subtracting Dgz. For implementation it has to be converted in an appropriate value Digz by equ. 19.
Valid ranges for the delay stages are:
Furthermore the delays of the processing elements are known. These are Doa = 1 for the adder and Dog = 1 for the gain. Equation 17 has to be stated more precisely for this example in:
|SDS = Dgxk + Dgsz + Dgz||(21)|
This linear optimisation problem can be simple solved via algebra programs. The solution is:
Dgxk = Dgsz = 0 and Dgz = 1. With n = 16 and respect to equ: 19 Digz = 15. That means only the delay block contains additional delay stages.
As already mentioned at the introduction of the bit serial approach, each bit needs one clock cycle for transmission and processing. Therefore it is not possible to implement an algebraic loop. Since this would be require Dgz = 0 in the example, which is not a solution of the minimizing problem however.
Thomas Reinemann 2003-07-03