Synchronization

In this place synchronization means aligning bits to the same significance and marking any bit of an operand. Generally, hardware solutions execute parallel information processing. Therefore different signal chains can lead to different delays. That means, a certain operator can receive operands with different delays.

Figure 5: Sync-Signals

For bit parallel processing, the significance of a bit is determined by the transmission line. However, if transmission is bit serial, then another method is needed to determine significance. Generally, various bits have to be labeled, depending on a certain algorithm and signals with different delays have to be synchronized. As a consequence it is necessary to mark any bit of an operand. Furthermore, a result can grow to n+1 or more bits, on certain operations, e.g. an addition or multiplication. Since the frame available for transmitting operands is constant, it has to take care that the operands are fitting within this frame. Therefore it is necessary to create a possibility to mark certain bits for an error treatment.

Accordingly, there is a bus with a width of n. A signal becomes active only for one clock cycle on each line. This offers a possibility to label any bit of the word, what happens by passing the signal's delay to the component. With this information a unit selects a given Sync-signal from the bus as given for example by equ. 4.

Depending on the known signal's delay it is possible to detect a difference of delays within a component, which has more than one input. The difference can be used to insert additional delay stages in the less delayed data stream (see figure 6). This method provides a simple way to synchronize data streams, if necessary.

Figure 6: Principle structure of a two inputs component

It is difficult and fault-prone to quantify delays manually especially for feed back loops. Since, an input's delay depends on its output's delay here. However it is possible to establish an equation system (equ.: 18), which contains the dependencies of the signal delays D_sx ( D_sui manipulated variable in fig. 4), the constant delays of the operators D_ox ( D_oa adder delay) and additional delay stages D_gx ( D_gxk, D_gsz at adder) needed for synchronization in the operators. This is linked with a set of valid ranges for the delay stages and a sum over all of them:

$$\sum_{i=0}^{n}$$ (17)

can be used to find a solution via minimization methods see (Bronstein, 1991). Quantifying the delays shall be shown by an example for the integrator shown in fig. 4.

$$\begin{split}D\sb{sui}&=D\sb{sz}+D\sb{gsz}+D\sb{oa} D\sb{sxk}&=D\sb{sx}+D\sb{og} D\sb{sz}&=D\sb{sui}-D\sb{gz} \end{split}$$ (18)

The delay block has the task to delay a sample for one clock period. Therefore the output's signal delay would be greater than the processing word width n and leads to additional delay stages at the other adder's input. This can be avoided by aligning to the prior word via subtracting D_gz. For implementation it has to be converted in an appropriate value D_igz by equ. 19.

D_igz = n - D_gz (19)

Valid ranges for the delay stages are:

Dgxk $$\geq$$ 0	Dgsz $$\geq$$ 0
0 $$\leq$$ Dgz $$\leq$$ 16	Dsuik $$\geq$$ Dsx

(20)

Furthermore the delays of the processing elements are known. These are D_oa = 1 for the adder and D_og = 1 for the gain. Equation 17 has to be stated more precisely for this example in:

S_DS = D_gxk + D_gsz + D_gz (21)

This linear optimisation problem can be simple solved via algebra programs. The solution is:

D_gxk = D_gsz = 0 and D_gz = 1. With n = 16 and respect to equ: 19 D_igz = 15. That means only the delay block contains additional delay stages.

As already mentioned at the introduction of the bit serial approach, each bit needs one clock cycle for transmission and processing. Therefore it is not possible to implement an algebraic loop. Since this would be require D_gz = 0 in the example, which is not a solution of the minimizing problem however.