Problems implementing controller and filter algorithms

Presently, digital signal processing is dominated by micro controllers and digital signal processors. Categorically, these systems must satisfy the Shannon theorem of sampling (Föllinger, 1993). This means, the sample frequency f_S has to be twice the maximum frequency occurring in the controlled system. These real time demands necessitate task execution in a limited time. Since some processor resources are only available once, they have to be shared between different tasks. Management of these resources is handled usually by a real time operating systems (Gray, 1999), (Kopetz, 1998). But high frequency signal processing increases the software overhead dramatically and consumes a too big amount of the processor's performance. As a result, a faster and often more expensive processor is needed in many cases.

Hardware like FPGAs or ASICs comes into operation for higher sampling rates. It offers a  possibility to perform signal processing in a parallel manner. This means signal flows are processed simultaneously, a delay results only from the longest chain but not from the sum of all chains, as using processors.

However, some obstacles handicap the usage of hardware:

• it needs different knowledge implementing algorithms in this manner than using software
• hardware description languages (HDL) have been made for circuit designers but not for mechatronic engineers, who prefer signal flows
• missing of general function libraries. Only very simple functions (addition, subtraction) are available, therefore more complicated functions have to be designed by the applicator itself.

Simulation of hardware is more sophisticated than software. HDLs like VHDL allow the description of test environments, too. Since they are powerful languages they are more flexible than a specific processor simulator, which world ends on its pins.