An Approach for delay optimization for gate level implementation of high speed controllers and filters

Roland Kasper and Thomas Reinemann

 

 

Abstract:

Today, improving a product often results in an increasing demand on its information processing capabilities. Especially in high dynamic systems these demands could be satisfied for a long time only by high speed micro controllers or signal processors. However these are very complex and expensive devices. In many applications real time operating systems come along to meet the real time requirements. These generate an additional overhead, which consumes further resources. Furthermore, it is not simple to make a clear prediction concerning the whole system performance. A more and more interesting alternative is given by FPGAs, which offer a very high speed at a price of a cheap controller. Furthermore, it is possible to make a clear prediction of the processing speed and timing. However, some obstacles are handicap the usage of ICs. The new approach presented in this paper is to transmit and process data in a bit serial manner. Therefore, a component processes only one bit during one clock cycle. This leads to very simple and fast processing elements. A library with the most common components has been built, which are needed for implementing controllers and filters, e.g. addition, subtraction, gain, multiplication, integrator, characteristic curve and so on. Presently, work runs on a simpler quantifying of signal delays.





Thomas Reinemann 2003-07-03